UK DHFCS 16289.5 kHz Follow-up: DRS GA-205 TDM Evidence and 1536-bit Frame Analysis

Following up on the initial analysis of the UK Defence High Frequency Communications Service (DHFCS) transmissions on 16289.5 kHz [1] (observed in both 800 Bd / 800 Hz FSK and STANAG-4285 modes), further analysis of extended raw bitstream captures has provided concrete evidence regarding the deployment of the Leonardo DRS GA-205 Time Division Multiplexer (or a fully compatible framing engine) and additional structural characteristics. The 1536-bit period bitstreams were obtained by demodulating some STANAG-4285 recordings from my personal repository. 

1. DRS GA-205 Synchronization character
All examined bitstreams share the exact same 16-bit synchronization sequence — referred to as the "Synchronization character" — specified as 9C16 (hex) in the DRS GA-205 TDM datasheet for Frame Type 1 (Figure 1) which is user-programmable depending on the selected operational profile. In this context, DRS refers to Leonardo DRS (formerly DRS Technologies), a major defense contractor specializing in tactical military communications, naval digital networks, and signal processing hardware. Specifically, the DRS GA-205 is a 12-channel Time Division Multiplexer (TDM) widely deployed across NATO and Allied naval assets [2].

Figure 1: Excerpt from the DRS GA-205 datasheet showing the synchronization character specifications

In binary format, the hexadecimal value 0x9C16 corresponds to the 16-bit sequence 1001110010011100 (MSB Most Significant Bit first). When transmitted over the air in standard LSB-first (Least Significant Bit first) bit order, it translates to 0011100100111001. According to the manufacturer's specifications, this synchronization sequence is user-programmable per frame type (e.g., 9C16 for Frame 1 or 9D16 for Frame 2). Figure 2 illustrates an example of this alignment within the demodulated bitstream.

Figure 2: Alignment of the 1536-bit periodic stream showing the vertical synchronization column matching the DRS GA-205 Frame 1 sync character (9C16 / LSB 0011100100111001)

1.1 Framing Lock Mechanism
The receiving framer scans the incoming bitstream for the static, known 16-bit sequence (0x9C16). Its sole purpose is to establish word alignment at the start of the frame and determine bit clock timing, operating completely independently of the subsequent frame layout.
The persistence of the identical 9C16 sync character across bitstreams with varying overall internal layouts highlights a fundamental design principle of the DRS GA-205 architecture: the decoupling of Bit/Frame Alignment from Payload Demultiplexing. While the static 16-bit sync word ensures immediate physical-layer framing lock across all transmissions, the underlying TDM engine adapts the 1536-bit frame structure and sub-field distribution to match the active user port allocations.

2. 1536-bit bitstreams
Although these 1536-bit period bitstreams rely on the exact same 9C16 sync character for primary frame alignment, their internal structures may differ significantly. For instance, certain layouts do not lend themselves to straightforward structural description or tabular breakdown, as illustrated by the complex bitstreams shown in Figure 3. 

Figure 3: Examples of 1536-bit period bitstreams exhibiting highly complex or irregular sub-framing structures despite sharing the identical 9C16 primary synchronization sequence.

Conversely, other bitstreams — such as the one shown in Figure 4 — feature a highly regular structure that can easily be mapped and detailed using simple tables (Table I).

Figure 4:  Bitmap representation of a highly regular 1536-bit STANAG-4285 bitstream divided into 21 sub-blocks, highlighting alternating 48-bit payload fields (D) and static 16-bit filler/separator fields (F)

Table I: Structural breakdown of the 1536-bit frame layout shown in Figure 4

The bitstream shown in Figure 4 can be directly compared with the one analyzed in the previous post [1], reproduced in Figure 5 along with its structural breakdown (Table II) for convenience.

Figure 5: Asymmetric 1536-bit STANAG-4285 frame layout from the previous post [1], divided into 7 main sub-blocks with variable field lengths (F1,​D1-F5,​D5​).

Table II: Detailed structural breakdown of the 1536-bit frame layout shown in Figure 5

2.1 Channel Interleaving vs. Hardware Ports

A potential point of confusion when analyzing these bitstreams is the presence of up to 21 distinct sub-blocks (or "pseudo-channels") within a single 1536-bit frame, as in the bitstream of Figure 4, given that the DRS GA-205 is physically a 12-channel TDM.
The 12 channels of GA-205 correspond to the 12 physical input ports, which are not transmitted as 12 monolithic blocks. When user ports are configured for different baud rates (e.g., mixing 75 Bd and 300 Bd channels), higher-speed channels are assigned multiple timeslots within the same 1536-bit macro-frame, naturally resulting in a sub-block count higher than the number of physical input ports.

To multiplex them into a single continuous stream, the TDM engine samples higher-speed ports multiple times per frame cycle while sampling lower-speed ports only once. Consequently, the 21 sub-blocks visible in the bitstream bitmap do not represent individual hardware ports, but rather the cyclical sampling sequence (interleaving ratio) of the TDM frame. Each sub-block carries its respective slice of user payload (D) alongside necessary framing, control, and pulse-stuffing overhead (F).
Conversely, Figure 5 displays only 7 main sub-blocks. This lower count indicates either that only a subset of the 12 hardware channels was active, or that multiple low-speed user ports were aggregated within shared timeslots.
Without access to the specific TDM preset configuration used in these captures, drawing definitive conclusions about the exact channel mapping remains challenging. In operational scenarios, these layout variations are recognized either via pre-configured operational profiles (where sender and receiver share a pre-set TDM channel mask) or via in-band framing status bits transmitted immediately following the very first sync header. Once the receiving framer locks onto 9C16, it applies the designated slicing mask to route each sub-field to its respective low-speed channel processor. It should be noted that, at least across the recordings currently in my repository, no identical layouts were found but rather streams that are merely "architecturally" similar.

3. Parallel fields (counters)
Direct text decoding of the parallel fields shown in Figure 6 (one 8-bit and two 7-bit fields) reveals that they do not function as dynamic numeric counters, but rather as deterministic ASCII test/idle pattern generators.

Figure 6: Bitmap alignment of the 1536-bit STANAG-4285 bitstream highlighting the position of three parallel sub-fields (cnt-1, cnt-2, cnt-3) within the TDM frame structure.

The decoded text (Figure 7) shows sequential progressions of the printable ASCII character set:

!"#$%&'()*+,-./0123456789:;<=>?\ABCDEFGHIJKLMNOPQRSTUVWXYZ(\)`ABCDEFGHIJKLMNOPQRSTUVWXYZ(~)\
!"#$%&"()*+,-./0123456789:;<=>?`ABCDEFGHIJKLMNOPQRSTUVWXYZ(|)~`ABCDEFGHIJKLMNOPQRSTUVWXYZ(~)

This behavior is characteristic of:
- Channel Integrity (BERT): Enables continuous Bit Error Rate (BER) measurement and frame loss detection across individual TDM sub-channels by stepping through the ASCII sequence at one character per frame.
- Idle Filler Sequence: Maintains symbol clock synchronization and bit transition continuity across the link when user ports are inactive or sending null traffic.

It should be noted that these behaviors, while consistent with the GA-205 architecture, are not necessarily exclusive to it, as similar idle/test patterns and interleaving schemes are common across many military-grade TDM systems.

Figure 7: Decoded ASCII text representation of parallel sub-fields, revealing continuous printable ASCII sequence sweeps used for channel integrity monitoring and alignment.

4. A Second Test Pattern: Baudot/ITA-2 Pangram Sequence
The following analysis is based on a separate demodulated bitstream capture, distinct from the ones used in Figures 1–10 above — a further illustration that, as already noted in Section 2.1, not all captured bitstreams share the same internal sub-block layout.
Reshaping the raw 1536-bit stream into a 12×16 byte matrix (12 rows×16 byte-columns per frame) reveals a striking pattern in column K (the 11th byte of each row) at same intervals, highlighted in Figures 8,9. Across 12 independently captured frames — each clearly identified by the recurring 0x3939 sync character in columns A and B (LSB-first of 0x9C16 sync character) — a total of 129 out of 144 cells (89.6%) in column K share the pattern "XXXXX111" consisting of trailing 3-bit suffix, whereas the leading 5 bits vary dynamically.

Figure 8: Bitstream visualization of the reshaped data frames. The white bounding box on the right highlights the recurring structural pattern observed at fixed byte intervals across multiple independent transmissions.

Figure 9: Part of the Excel matrix alignment (12×16 bytes) of consecutive 1536-bit frames, highlighting the primary sync header and the persistent XXXXX111 pattern in column K (11th byte).

Extracting the variable 5-bit prefix from each of these 129 bytes and decoding it as International Telegraph Alphabet No. 2 (ITA-2 / Baudot-Murray, CCITT-2) produces a clearly recognizable result:

"…THE QUICK BROWN FOX (JUMPS) OVER THE LAZY DOG…" followed by a FIGS-shifted digit run (0–9).

Independent decode of the same demodulated bitstream using dedicated RTTY/Baudot decoding software (5×19 multiplex, positive polarity, correct bit order). The software's raw output (top) closely matches the ITA-2 reading derived manually above (white box, overlaid for comparison), corroborating the "THE QUICK BROWN FOX..." pangram test pattern (Figure 10).

Figure 10: Decode of the same demodulated bitstream using dedicated RTTY/Baudot decoding software

This is the classic pangram test string long used to exercise teleprinter and RTTY equipment, as it contains every letter of the alphabet. Notably, the small gaps observed in the decoded text in Figure 10 (e.g., "QUIC" instead of "QUICK") coincide exactly with the row-1/sync boundary of each frame where the character stream is interrupted — providing independent confirmation of the frame's periodicity.
Taken together with the printable-ASCII BERT/idle sweep documented in Section 3 (from the primary bitstream), this demonstrates that different GA-205 captures can carry structurally distinct low-speed test channels — one bitstream multiplexing a 7/8-bit ASCII test sequence, and another multiplexing a 5-bit Baudot/ITA-2 test sequence. This strongly reinforces the mixed-rate channel interleaving model discussed in Section 2.1.

The byte-matrix reshaping, statistical pattern analysis, and ITA-2/Baudot decoding presented in this section were carried out with the assistance of Claude (Anthropic AI), based on raw demodulated bitstream data provided by the author.

5. 1024-bit bitstreams & GA-205
Bitstream analysis of demodulated 800 Bd / 800 Hz FSK recordings (Figure 11) revealed a 1024-bit frame period that shares the exact same sub-block multiplexing architecture as the 1536-bit STANAG-4285 streams, yet lacks the standard 0x9C16 sync word. Instead, these streams consistently exhibit a 11-bit (LSB) synchronization sequence: 01100001101.

 

Figure 11: Alignment of the 1024-bit FSK periodic stream displaying the 11-bit vertical synchronization sequence (01100001101)

 

As outlined in the manufacturer specifications, and illustrated in the preset screenshot in Figure 12, the DRS GA-205 synchronization character is not hardcoded; it is user-programmable depending on the active operational profile or frame configuration — e.g., Frame Type 1 using 0x9C16 vs. Frame Type 2 using 0x9D16, or even a custom user-defined vector such as 01100001101. Naturally, this configuration must be agreed upon and shared between peers prior to transmission.

 

Figure 12: GA-205 TDM software control interface showing configurable aggregate parameters, sync code options, and individual user port rate allocations

6. Conclusions
To ground these bitstream findings in real-world military infrastructure, we must examine the hardware lineage and strategic deployments behind these transmissions. Specifically, looking at two major industrial partnerships highlights how the Leonardo DRS GA-205 Time Division Multiplexer is integrated across NATO and Allied HF network.

- Australian Defence Force (ADF) & MHFCS (Bellinger Systems):
In Australia, Bellinger Systems (a SYPAQ subsidiary) signed a long-term agreement with Leonardo DRS to procure, integrate, and support the GA-205 modernisation and delivery program. This program includes delivering approximately 100 modernised GA-205 TDM units to the Australian Defence Force to support their Modernised High Frequency Communications System (MHFCS) and transition towards Link 22 tactical data link architectures [3] (1).

Figure 13: Dimensional specifications comparison between the modernised Bellinger Systems GA-205 (left) and the original DRS Technologies (right).

- UK Defence High Frequency Communications Service (DHFCS / Babcock International):

Within the UK DHFCS infrastructure, primary defense contractors and service partners (such as Babcock International) manage the strategic HF communication sites, ground stations, and ship-to-shore links. In these strategic architectures, the GA-205 TDM serves as the key bridging multiplexer, interfacing legacy low-speed user channels with high-speed HF modems across UK Defence HF networks.

While absolute confirmation would require declassified operational documentation, there is strong circumstantial and technical alignment between the observed sub-block structures and the GA-205’s native support for the U.S. Navy High Speed Fleet Broadcast (HSFB) architecture(2). Designed specifically to aggregate heterogeneous low-speed naval messaging and tactical data streams over a single HF carrier, the HSFB framing profile provides a compelling explanation for the rigid slot allocation and deterministic frame synchronization observed across both STANAG-4285 and FSK transmissions in the DHFCS/MHFCS networks.

Notes

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1. The dimensional discrepancies between the original DRS datasheet (standard 1U 19-inch rackmount) and Bellinger Systems' product sheet (200×132×620 mm) strongly point to a modernised form-factor evolution. Bellinger re-packaged the GA-205 TDM engine into a modular ATR-style / vertical-rack footprint for the Australian Defence Force's MHFCS project, integrating internal flash-upgradable firmware, higher aggregate data rate handling (up to 38.4 kbps), and built-in Link Local Controller (LLC) support for modern naval communication racks.

2. The U.S. Navy High Speed Fleet Broadcast (HSFB) is a U.S. Navy and NATO hardware architecture for shore-to-ship multi-channel fleet broadcast communications. HSFB replaced older single-channel low-speed (75-baud) broadcast links by aggregating multiple heterogeneous low-bitrate channels into a unified TDM stream over HF/UHF carriers. Native HSFB support within the Leonardo DRS GA-205 multiplexer ensured multi-channel broadcast interoperability across Allied naval communication networks (US Navy, UK DHFCS, and RAN MHFCS).

 

References

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[1] 800Bd/800Hz (critical) FSK and STANAG-4285 Transmissions http://i56578-swl.blogspot.com/2026/08/800-bd-800-hz-critical-fsk-and-stanag.html
[2] Leonardo DRS, GA-205 Time Division Multiplexer datasheet — cleared for public release under OSR case no. 05-S-0976 (08.25.2007) https://www.leonardodrs.com/wp-content/uploads/2023/08/ga205.pdf
[3] https://www.sypaq.com.au/news/sypaq-subsidiary-bellinger-signs-historic-agreement-with-leonardo-drs/