I
have some doubts about the description at page 19 of MIL 188-203-1A
(Tadil-A/Link-11) [1]: the document states that the Start Code and the
Address Code frames " [...] are equivalent to 60-bit portions of the maximum-length shift register sequence with generator polynomial G(x) = x5+x+1" ...but such a fifth grade polinomyal has a maximum length sequence (MLS) of 31 bits (25-1). Indeed, I found the generator polymonial x6+x+1, whose MLS is 63, for both start and address frames:
111100101000110000100000111111
101100110111011010010011100010
100001000001111110101011001101
110100100111000101111001010001
101100110111011010010011100010
100001000001111110101011001101
110100100111000101111001010001
Using a GNU Octave script [2] I also checked the three fundamental properties of LFSR maximum length sequences: Balance Property, Runlength Property, and Autocorrelation Property [3]: verification fails for x5+x+1
- The Code does NOT satisfy Balance Property: number of 1s and 0s are 17 14
- The code does NOT satisfy RUN LENGTH property: the run length is 10 2 1 1 2
- The Code does NOT satisfy the Autocorrelation Property
- The Code satisfies Balance Property: number of 1s and 0s are 32 31
- The code satisfies RUN LENGTH property: the run length is 16 8 4 2 1 1
- The Code satisfies the Autocorrelation Property
So I do not know if I'm wrong or if there's a typo in 188-203-1A, comments are welcome.
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