MS188-110 scrambler lenght and ACF (another test)

13 February 2016

MS188-110 scrambler lenght and ACF (another test)

In a previous post I already talked about the way MS188-110 scrambler length affects the value of the ACF and only at certain data rate speeds, today I wanted to verify this matter but using a bitstream analyzer rather than SA.

In order to do that, I needed to pick up transmission symbols from the output of the scrambler, just before the PSK-8 modulator: i.e. the "pure" symbols flow, without any other addition such as mini-probes or preamble re-insertions. In other words, I needed a sort of reduced MS188-110 modem as shown in pic . 1

pic. 1 the reduced MS188-110 modem

Since this kind of reduced-modem simply doesn't exists, I decided for a software-implementation by writing a simple LUA [1] program, following the directions provided by the protocol [2] (see below): the program doesn't use bitwise operations but handle binary values as array of ASCII zeroes and ones such as {101} for 0x101. Since the scope, FEC Encoder and Interleaver matrices have been omitted and replaced by a binary input file (formed of random binary data) and/or a constant binary data string.

As said, known data sequences (mini-probes) and preamble re-insertions have also been omitted just to prevent ACF periods due to these patterns.

5.3.2.3.8 Scrambler.
The tribit number supplied from the symbol formation function for each 8-ary transmitted symbol shall be modulo 8 added to a three bit value supplied by either the data sequence randomizing generator or the sync sequence randomizing generator.

5.3.2.3.8.1 Data sequence randomizing generator.
The data sequence randomizing generator shall be a 12 bit shift register with the functional configuration shown on figure 6. At the start of the data phase, the shift register shall be loaded with the initial pattern shown in figure 6 (101110101101 (binary) or BAD (hexadecimal)) and advanced eight times. The resulting three bits, as shown, shall be used to supply the scrambler with a number from 0 to 7. The shift register shall be shifted eight times each time a new three bit number is required (every transmit symbol period). After 160 transmit symbols, the shift register shall be reset to BAD (hexadecimal) prior to the eight shifts.

As shown in pic. 1, the software output is a bitstream file called "scrambler-output.txt" that can be analyzed through a bit analyzer, and here we are: the result is shown in pic. 2., as it was to be expected, and incidentally reported in MIL 188-110 standard, the scrambler just produces a periodic pattern 480 (160 transmit symbols) bits in length!

pic. 2 - 480 bits (160 PSK-8 symbols) period

So, summarizing what has already been written in the cited post, this is why at low data-rate speeds (from 150 up to 1200 bps) the ACF analysis produces strong 66.67ms spikes (pic. 3): four contiguous groups of the pairs [mini-probe] + [unknown data] makes 160 symbols (pic. 4) and they are just in sync with the scrambler length! At lowest speed (75bps) there are no channel probe so the 66.6ms ACF is only due to the scrambler.